In generic micro-processor design, I/O blocks are typically supported with a separate supply voltage and the processor does not have a way to control I/O functionality. Even with an internal stand-by with I/O idling capabilities, voltage leakage is inevitable in the I/O block. This anomaly is amplified when a processor has many I/O blocks for an I/O intensive design. Many current products have this implementation, and, thus, power consumption cannot be well managed. That is, existing I/O blocks may consume up to 50% of the total power for an I/O intensive application. Moreover, processor I/O circuits may drain 25-50% of the total power in this design approach even when the system is in idle mode.
In view of the foregoing, there exists a need for an approach that overcomes at least one of the deficiencies in the existing art.